TapeGenius
CHALLENGE 001 / GENESIS

Small core.
Open possibilities.

Your first architecture. A place to explore what silicon can become.

Design your Genesis
INPUT AI/O INPUT BI/O DECODECONTROL / X2REGISTERSMEMORY / X2VECTOR ALUCOMPUTE / X2L1 SRAMMEMORY / X2ACCCOMPUTE / X2OUTPUTCONTROL / X2OUT AI/O OUT BI/O TapeGeniusGENESIS / SC-01
SC–01 / THE DESIGN BRIEF

Bring a core
to life.

Two input banks. Six functional blocks. Two outputs. Shape the interconnects, tune the modules and find your own balance of timing, area and power.

10blocks
18interconnects
1,200cell budget
GENESIS / COMPETITION ENTRY

Pay once. Submit unlimited versions. Your highest score counts.

300,000tokens / round
01 / EXPLORE

One chip.
Three ways of seeing.

Floorplan shows the regions and cell texture of your design. Signal view illuminates the interconnect fabric. Power view colors each module by its configured drive strength. The schematic lets you rearrange and connect the underlying blocks.

02 / MAKE A DESIGN

More drive.
More tradeoffs.

Higher drive strength reduces modeled block delay while increasing cell area and power. Wider interconnects reduce wire delay and use more area. Routing bias influences which allowed signal path is chosen. Presets give you starting points; every parameter remains yours to explore.

Keep all four input-to-output traces connected and stay within the 1,200-cell area budget to enter the leaderboard or create a tapeout artifact.

03 / COMPETE

A shared design score.

45%TimingShorter modeled critical signal path
30%AreaLess of the fixed cell budget used
25%PowerLower design power index

Entry costs 300,000 tokens per round on BNB Smart Chain. Pay once to unlock unlimited submissions for this round. Submit more versions as you refine your design; your highest score counts. No closing time has been set.

About the design model

TapeGenius is a visual chip-design playground. Scores use a deterministic game model of block drive, interconnect delay, area and power. The visuals are procedural representations of your settings. They are not transistor simulation, measured thermals, functional logic verification or fabrication-ready layouts.

Exact scoring rules

Timing = max(0, 100 − 4 × critical path delay). Area efficiency = max(0, 100 × (1 − cells / 1,200)). Power efficiency = max(0, 100 − power index / 3). Each is rounded to two decimals, then the weighted sum is multiplied by 100 and rounded. Details are implemented in the shared server model, silicon-play-1.

Wallets, tapeout and ownership

A verified entry payment to the treasury unlocks this round for your wallet. Submit and refine as many versions as you like. Virtual tapeout generates a digital chip artwork saved on your device. It does not mint an NFT or manufacture a physical chip. Your chip collection is independent of competition entry.

FROM AN IDEA TO SOMETHING YOU CAN SEE.Make your mark.