TapeGenius
TapeGenius / GENESIS WORKSPACE

Design studioGenesis / SC–01

Draft · Not submitted
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TUNING PRESET
GENESIS● Open
0 submitted versionsRound best Your versions ↓
CHIP EXPLORERSelect a module · Make it yours
GENESIS / 10 BLOCKS SELECT A REGION TO EXPLORE
INPUT AI/O INPUT BI/O DECODECONTROL / X2REGISTERSMEMORY / X2VECTOR ALUCOMPUTE / X2L1 SRAMMEMORY / X2ACCCOMPUTE / X2OUTPUTCONTROL / X2OUT AI/O OUT BI/O TapeGeniusGENESIS / SC-01
100%

Pick a tool. Touch the silicon. View and lighting changes do not affect your score.

COMPUTE · MEMORY · CONTROL · I/OSC–01 / SILICON EXPLORER
Signal fabric Metal layers16 / 18 active
SIGNAL TRACE 4 I/O paths
F01S1 T1Run analysis to illuminate this trace
F02S1 T2Run analysis to illuminate this trace
F03S2 T1Run analysis to illuminate this trace
F04S2 T2Run analysis to illuminate this trace
YOUR CHIP BENCH / TOP 20 ON THIS DEVICE

Keep experimenting. Keep your best.

Valid runs stay here, ranked by score. Load a chip to continue shaping it. These are practice runs, not final submissions.

Run your first chip to start your bench.

DESIGN REPORT

Build it. Light it up. Make it yours.

Explore a visual chip model, then turn the result into your own virtual tapeout. Model details are in the Genesis challenge.

I/O connectivityAwaiting analysis
Power indexAwaiting analysis
BudgetAwaiting analysis
ConfigurationHashed by the server